Optimization of Crosstalk Delta Delay on Clock Nets – Design and Reuse

By Shailesh Kumar, Jaya Patel, Meetu Sharma, and Rajendra Pratap Singh (eInfochips (An Arrow Company))


As chip size decreases the standard cell density and routing density of the design increases, due to that metal routes may interact with each other and it may result in a coupling effect which is known as crosstalk. It affects both signal nets as well as clock nets. In this paper, we would analyse the causes of high crosstalk delta delay on clock nets and find an automated way to take care of the crosstalk delta by applying single-width double-track NDR on clock nets at an early stage of the design cycle.


Standard cell, coupling effect, delta delay, NDR, crosstalk.


The design process of a chip plays a very important role in any device. There are three things that we have to optimize on a chip, they are Power, Performance, and Area.

The power consumption on a chip should be as low as possible, performance should be high and mostly a smaller area is preferred. As we go for the lower technology node, the lateral capacitance between two nets in a chip dominates than interlayer capacitance. Hence, capacitive coupling formed between two nets is the main reason for the functionality failure of a chip. Crosstalk is one of them.

If any logic is transmitted through a net that affects another neighbouring net due