Startup develops novel transistor for low power – eeNews Europe

The company was formed in 2017 by Professor Asen Asenov, former CEO of Gold Standard Simulations Ltd. (GSS), a leader in variability CMOS simulations and variability-aware technical CAD.

Semiwise’s first offering is something called the flat field transistor (FFT). It is applicable to bulk CMOS manufacturing processes down to 20nm and suited to Internet of Things and on-chip artificial intelligence operations, Asenov claims.

Applied to 20 nm bulk CMOS the FFT has 30 percent higher speed performance and two orders of magnitude lower leakage current at equivalent drive current compared to its bulk counterpart the company said. The far field transistor configuration was designed using GSS – now Synopsys – variability-aware TCAD tools. It has low variability with factors in the range of 0.6mV/micro, which is much lower than the reported variability for 14nm FinFET and 28nm FDSOI manufacturing processes.

The low variability of the FFT means that guard-banding on numerous design parameters can be reduced and makes the transistor suited to near and sub-threshold logic and low-voltage tolerant SRAM design, the company claims.

“The concept of variability resistant transistors has been around for a few years however despite significant venture capital investments many companies have failed to commercialise the technology due to lack of firm understanding of statistical variability and adequate simulations capabilities,” said Asenov, in a statement. “Armed with the most accurate and reliable simulation tools from GSS – now Synopsys – and more than 35 year of experience in the semiconductor industry Semiwise will succeed when others have failed.”

Semiwise
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